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Michael Scott
Results: 777

#	Item
291	ASPLOS 2010 poster session Hybrid TM Using NOrec STM Luke Dalessandro, URCS; Michael Spear, Lehigh Michael Scott, URCS "Ideal" HTM Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2011-04-10 16:11:27 Politics Foreign relations Government OREC Rice Parallel computing
292	IEEE TRANSACTIONS ON SOFTWARE ENGINEERING, VOL. 14, A Simple Mechanism for Type Security Across Compilation Units MICHAEL L. SCOTT Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2004-06-23 16:50:23 Data types Hashing Search algorithms Error detection and correction Hash function Pointer Cryptographic hash function C Array data type Computing Software engineering Computer programming
293	Butterfly Project Report 7 LYNX Reference Manual Michael L. Scott Revised Version: August 1986 Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2011-03-24 17:07:44 Procedural programming languages Compiler construction Programming language implementation ALGOL 68 Regular expression C Switch statement D Software engineering Computing Computer programming
294	A SIMPLE MECHANISM FOR TYPE SECURITY ACROSS COMPILATION UNITS by Michael L. Scott Raphael A. Finkel Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2011-03-26 00:09:34 Data types Error detection and correction Hashing Procedural programming languages Search algorithms Hash function C Pascal Forward declaration Computing Software engineering Computer programming
295	The Energy Impact of Aggressive Loop Fusion ∗ YongKang Zhu? , Grigorios Magklis‡ , Michael L. Scott† , Chen Ding† , and David H. Albonesi? ? Department of Electrical and Computer Engineering † Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2004-09-22 15:49:25 Computer programming CPU cache Loop optimization Parallel computing Cache Loop fission Software pipelining Infinite loop Loop fusion Compiler optimizations Computing Software engineering
296	Nonblocking Transactions Without Indirection Using Alert-on-Update ∗ Michael F. Spear, Arrvindh Shriraman, Luke Dalessandro, Sandhya Dwarkadas, and Michael L. Scott Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2007-03-22 21:05:08 Computing Data Software transactional memory CPU cache Linearizability Lock Database Extensible Storage Engine Redo log Transaction processing Data management Concurrency control
297	Scalable Synchronous Queues ∗ William N. Scherer III Doug Lea Michael L. Scott Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2006-02-10 21:14:46 Concurrent computing Computer programming Scheduling algorithms Tree traversal Inter-process communication Queue FIFO Monitor Stack Abstract data types Computing Concurrency control
298	strategy+business Best Business Books 2007 by Michael Schrage, David Newkirk, Joe Flower, Diane Coyle, Tom Ehrenfeld, Howard Rheingold, R. Gopalakrishnan, and James O’Toole Add to Reading List Source URL: www.strategy-business.com Language: English - Date: 2007-11-18 21:02:51 Innovation Scott Berkun Science Joseph Schumpeter Creative destruction Structure Design Technological change Economics
299	Tech. Rep[removed]Software Cache Coherence for Large Scale Multiprocessors Leonidas I. Kontothanassis and Michael L. Scott Department of Computer Science University of Rochester Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2011-03-27 22:55:06 Cache coherency Parallel computing Computer memory Central processing unit Cache coherence CPU cache Shared memory Cache Distributed shared memory Computing Concurrent computing Computer architecture
300	CCC Wkshp. on Advancing Computer Architecture Research (ACAR): What Now in ILP?, Seattle, WA, Sep[removed]In Search of Big Instructions Arrvindh Shriraman, Sandhya Dwarkadas, and Michael L. Scott Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2011-04-01 17:49:01 Central processing unit Classes of computers Parallel computing Microprocessors Microarchitecture Superscalar Reduced instruction set computing Instruction-level parallelism Very long instruction word Computer architecture Computing Computer hardware

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